A typical semiconductor memory comprises an array of memory cells on an integrated circuit (IC) chip. The memory cells of a typical memory array are in a matrix of rows and columns, with each row including multiple cells, one in each column; one cell in each row is for each bit of a word stored in the row. It is often desirable to selectively mask one or more of the memory cells to prevent the masked cells from being read.
Reading conventional addressable memory cells is by cell addresses, while content addressable word memory (CAM) cells are read by comparing cell contents with a reference bit. CAM cells are of the single and dual port type; dual port CAM cells increase the flexibility of memories including CAM cells.
FIG. 1 is a circuit diagram of a known dual port CAM cell 10 including a masking arrangement in a static random access memory (SRAM) array. CAM cell 10 includes SRAM storage cell 12 which stores a single data bit at a time, but which can respond at different times to two data bit sources IN1 and IN2. Dual port CAM cell 10 also includes two write ports 32, 34, two read ports 36, 38, two matching (i.e., comparing) circuits 40, 42 responsive at different times to reference bits CN01 and CN02, and two match output lines 68, 69 respectively driven by circuits 40, 42.
Cell 10 can be used as a conventional memory cell or as a CAM cell. When cell 10 is used as a conventional memory cell and is not masked, ports 36, 38 derive levels indicative of the value of the bit that cell 10 stores. When cell 10 is used as a CAM cell and is not masked, lines 68, 69 derive levels indicative of whether the value of the bit cell 10 stores is the same or differs from a reference bit applied to the cell. When cell 10 is masked, cell 10 does not supply any signals to ports 36, 38 and lines 68, 69, so voltage levels at these ports and lines are static.
Cell 12 includes a first data storage node 14 and a second data storage node 16 for normally storing complementary data values, e.g., node 14 stores a logic high INH1 and node 16 stores a logic low INL1 in response to IN1 having a high value. Cell 12 includes a first inverter 17 formed by a pair of complementary field effect transistors (FETs) 18, 20 and a second inverter 21 formed by a pair of complementary FETs 22, 24. The complementary FETS of each of inverters 17 and 21 have (1) series connected source drain paths connected between a DC power supply voltage, +V.sub.DD and ground, (2) gate electrodes that are driven in parallel by a bi-level input signal, and (3) drain electrodes tied to a common terminal that is the inverter output. The first and second inverters 17 and 21 have cross-coupled inputs and outputs to thereby form a latch in a known manner. The input of inverter 17 and output of inverter 21 are tied to storage node 14, while the output of inverter 17 and the input of inverter 21 are tied to storage node 16.
Storage nodes 14, 16 of cell 12 are respectively connected via first and second data lines 28 and 30 to input terminals of ports 32-38 and matching circuits 40, 42. Write ports 32 and 34 include pass gate N-channel FETs. Write port 32 is responsive during a first write operation to the complementary binary data values INH1 and INL1 and write port 34 is responsive to complementary binary data values INH2 and INL2. The first and second write operations occur at different times. Read ports 36 and 38 respectively respond during different read operations to high voltage values of dump pulses, DUMP I and DUMP 2, which are derived at different times. Read ports 36 and 38 supply complementary binary values on lines 28 and 30 to complementary output leads OUTL1 and OUTH1 when a pulse DUMP1 is derived and to complementary output leads OUTL2 and OUTH2 when a pulse DUMP2 is derived.
Matching circuit 40 responds to complementary binary reference bits CNOL1 and CLOH1, indicative of a bit whose value is selectively compared with the value of the bit stored in cell 12; bits CNOL1 and CNOH1 are applied to lines 64 and 66 and are derived by circuitry (not shown) in response to CNO1. When cell 10 is not masked (i.e., is unmasked), matching circuit 40 compares the bit value stored in cell 12 with the value of the reference bits CNOL1 and CNOH1 bits to signal if the stored and reference bits have the same value. Matching circuit 42 performs the same operations as circuit 40, but responds to complementary reference bits CNOL2 and CNOH2. The comparing operations matching circuits 40 and 42 perform provide cell 10 with the CAM capability.
CAM cell 10 also includes a latch 44 including inverters 47 and 49 having the same elements, connections and back-to-back arrangement as inverters 17 and 21. Latch 44 latches one of mask bits, MASK1 or MASK2. The mask bits have binary one and zero values for respectively masking and unmasking cell 10. A first mask bit write port 50 and a second write bit mask port 52 respectively respond to MASK1 and MASK2 to write the mask bit value into latch 44. Mask bit MASK1 is represented by complementary bits, MASKH1 and MASKL1. Bits MASK1 and MASK2 are coupled to the latch 44 when SET1 is high, while MASKH2 and MASKL2 are coupled to latch 44 when SET2 is high.
Control line 54 responds to the mask bit voltage value stored at node 45 to control masking of cell 12. Line 54 applies the mask control voltage associated with the stored mask bit in parallel to the gate electrodes of masking control FETs 56, 58 and 60 of cell 12, to control the mask and unmask operations of cell 10. FET 56 has a source drain path between power supply terminal +V.sub.DD and the source drain paths of FETs 18 and 20 of inverter 17 and the source drain paths of FETs 22 and 24 of inverter 21. The source drain paths of FETs 58 and 60 respectively sink the source drain paths of FETs 18 and 20.
In response to the mask bit at node 45 and on line 54 having a logic low (i.e., logic "0" as represented by the ground voltage of the chip DC power supply), CAM cell 10 is unmasked by the low voltage that line 54 applies to the gates of FETs 56, 58 and 60. The low voltage level carried by control line 54 turns on P-channel FET 56 and turns off N-channel FETs 58 and 60, to thereby configure cell 12 for normal, unmasked operation, enabling cell 12 to supply complementary data values (e.g., a logic low "0" and a logic high "1") to storage nodes 14 and 16. That is, while the mask bit at node 45 is a logic low, cell 12 operates as a standard, cross-coupled inverter latch responsive to the +V.sub.DD power supply voltage at the source of FET 56, as if FETs 58 and 60 were not included in the circuit.
During an unmasked CAM look-up operation, one of matching circuits 40 or 42 compares the bit values associated with the complementary bits stored in cell 12 to complementary reference bit values CNOL1 and CNOH1 or CNOL2 and CNOH2. If matching circuit 40 detects a match between the bits on data bit lines 28 and 30 and reference bit lines 64 and 66, a high voltage supplied by circuitry (not shown) to match line 68 is maintained and the MAT1 output of matching circuit 40 has a high value. If matching circuit 40 detects a mismatch between the reference and stored data bits, a low impedance of the matching circuit d(Lischarges the high voltage on line 68 and MAT1 has a low value.
Match line 68 is discharged through (1) a first pair of N-type FETs 70, 72 having series connected source drain paths between match line 68 and the CAM ground rail, or (2) a second pair of similarly configured FETs 74, 76. Matching circuit 40 is arranged such that if the above-mentioned mismatch occurs, FETs 70, 72 are turned on simultaneously by high voltage levels respectively applied to the gate electrodes thereof via reference data line 64 and first data line 28. Matching circuit 42 responds in a similar manner to the bits on leads 28 and 30, as well as CNOL2 and CNOH2 to control the MAT2 voltage.
In contrast, while the stored mask bit at node 45 and on line 54 is a logic high (i.e., logic "1"), the matching operation of CAM cell 10 is masked to prevent discharge of MAT1 and MAT2 during a CAM look-up operation, even if there is a mismatch between reference bits CNOL1 and CNOH1 or CNOL2 and CNOH2 and the data bit that inverters 17 and 21 store. During masking, the high voltage level on control line 54 turns off P-channel FET 56, and turns on N-chainel FETs 58 and 60. The +V.sub.DD power supply voltage is removed from the FETs of inverters 17 and 21 and the source drain paths of FETs 58 and 60 respectively apply low impedances across the source drain paths of FETs 18 and 22 of inverters 17 and 21. Consequently, the source drain paths of FETs 58 and 60 apply the ground voltages at the source electrodes of these FETs to both nodes 14 and 16. The low voltage levels at storage nodes 14 and 16 thus no longer represent the data bit previously stored in cell 12.
The low levels at nodes 14 and 16 respectively drive the gate electrodes of N-channel FETs 72 and 74 to keep these FETs turned OFF. Because FETs 72, 74, are OFF, neither first FET pair 70, 72 nor second FET pair 70, 76 can discharge MAT1 or MAT2 to a low voltage, regardless of the reference data levels lines 64 and 68 respectively apply to the gates of FETs 70 and 76 of circuit 40 or the corresponding gates of circuit 42.
The flexibility offered by the dual port configuration of CAM cell 10 is seriously undermined by the disadvantages associated with requiring two write ports 32 and 34 and two mask ports 50 and 52. Mask ports 50, 52 respectively include a pair of mask bit input lines 80, 82 and 84, 86, which carry complementary values to mask bit latch 44. These four extra mask bit lines associated with selectively masking CAM cell 10 constitute approximately 25% of (1) the total number of data lines coupled with cell 10 and (2) the total amount of metal required for the cell data lines. Bit lines 80, 82, 84 and 86 also occupy a substantial fraction, nearly 25%, of the foot-print or overall area that cell 10 occupies on an integrated circuit chip.
The large fraction of metal and area resources taken up by the mask bit lines 80, 82, 84 and 86 seriously limits (1) the CAM array cell density, and (2) the metal pitch or width of the data lines connected to each array cell because the total number of data lines coupled to cell 10 is a dominant factor in determining the pitch of the data lines. Such limitations are especially acute in the dual port CAM of FIG. 1, relative to a single port CAM, because of the high total number of metal data lines used for accessing the dual port CAM cells.
Limiting the pitch of or narrowing the metal data lines on the integrated circuit disadvantageously increases the resistance and resulting resistance-capacitance (RC) time constants of such metal lines. Limiting the CAM cell array density causes individual CAM cells to be farther from each other in the array, to increase the length of interconnecting metal data lines which, in tunr, increases metal data line resistance and RC time constants. Such increases in data line RC time constants of the CAM cell array disadvantageously limit the operating frequency of the CAM cell array.
In summary, there is a need to reduce the total number of data lines coupled with each dual port CAM cell in a CAM cell array without reducing the capabilities of the dual port CAM cell to thereby increase CAM cell array density and operating frequency.